1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming an improved interface between a conductive via and a conductive contact structure by selective formation of a conductive capping layer.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area Immense progress has been made over recent decades with respect to increased performance and reducing the physical size (feature sizes) of circuit elements, such as transistors. Field effect transistors (FETs) come in a variety of configurations, e.g., planar transistor devices, FinFET devices, nanowire devices, etc. Irrespective of the form of the FET, they have a gate electrode, a source region, a drain region and a channel region positioned between the source and drain regions. The state of the field effect transistor (“ON” or “OFF”) is controlled by the gate electrode. Upon the application of an appropriate control voltage to the gate electrode, the channel region becomes conductive, thereby allowing current to flow between the source and drain regions.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured. Rather, integrated circuit products typically have one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is provided, a first lower end of which is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and a second end is connected to a respective metal line in the metallization layer by a conductive via. Such vertical contact structures are considered to be “device-level” contacts or simply “contacts” within the industry, as they contact the “device” that is formed in the silicon substrate. The contact structures may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. In other applications, the contact structures may be line-type features, e.g., source/drain contact structures.
FIGS. 1A-1H depict one illustrative prior art technique for forming contact structures for semiconductor devices. FIG. 1A is a simplified view of an illustrative prior art transistor device 10 at an early stage of manufacturing. The device 10 is formed in an active region of a semiconductor substrate 12 that is defined by a simplistically depicted trench isolation region 14. The device 10 also includes a schematically depicted gate structure 16, a gate cap layer 18 (e.g., silicon nitride), sidewall spacers 20, source/drain regions 22, a thin native oxide layer 13 (that is formed when the source/drain regions are exposed to air, and it may or may not be present in all situations) and an illustrative layer of insulating material 24. Although the layer of insulating material 24 is simplistically depicted as being a single layer of material, in practice, the layer of insulating material 24 may be comprised of a plurality of layers of insulating material, perhaps with an intervening etch stop layer formed between such layers of material.
FIG. 1B depicts the device 10 after one or more etching processes were performed through a patterned etch mask (not shown), such as a patterned layer of photoresist or a patterned hard mask layer, to define illustrative contact openings or trenches 26 in the layer of insulating material 24. The formation of the contact openings 26 normally exposes a portion of the source/drain regions 22. However, as depicted in FIG. 1C, as part of the contact formation process, a pre-clean process will normally be performed to remove any residual insulating materials, including the exposed portions of the native oxide layer 13 (when present) to insure that the upper surface of the source/drain regions 22 are exposed.
FIG. 1D depicts the device 10 after a schematically depicted barrier layer/adhesion layer 28 was formed on the device 10. In one embodiment, the barrier layer/adhesion layer 28 may be comprised of a first barrier layer of titanium nitride and a second adhesion layer made of diborane (B2H6), both of which may be formed by performing sequential conformal deposition processes, e.g., atomic layer deposition (ALD), etc. After the barrier layer/adhesion layer 28 is formed, a conductive material layer 30, such as tungsten, is formed in the contact openings 26. As depicted, in many situations, a schematically depicted seam 31, or vertically oriented void, will form in the contact openings 26. The seam 31 is believed to form because the openings 26 tend to “pinch-off” when it is filled. The layer of insulating material 24 may be comprised of a variety of different materials, e.g., silicon dioxide, etc., and it may be formed to any desired thickness. The conductive material layer 30 may be comprised of a variety of different metals or metal compounds, e.g., Ti, W, Mo, Co, TiN, Al, etc.
FIG. 1E depicts the device 10 after one or more chemical mechanical polishing (CMP) operations were performed to remove the excess amounts of the barrier layer/adhesion layer 28 and the conductive material layer 30 positioned outside of the contact openings 26. These operations result in the formation of conductive contacts 32 in the contact openings 26. As depicted, portions of the seam or void 31 remain in the contact 32, and an opening 33 to the interior of the void 31 may be present.
FIG. 1F depicts the device after several process operations were performed. More specifically, an etch stop layer 40, a layer of insulating material 42 and another etch stop layer 44 were deposited above the structure depicted in FIG. 1E. Thereafter, various openings 41 for various metallization structures were defined in the layers 40, 42 and 44 by performing known etching and masking process operations. The openings 41 expose the contacts 32 and the void 31 formed therein.
Next, as shown in FIG. 1G, a schematically depicted barrier layer/adhesion layer 46 was formed across the device and in the openings 41. In the case where copper metallization layers will be formed for the device, the barrier layer/adhesion layer 46 may be comprised of a first barrier layer of tantalum nitride (TaN) and a second adhesion layer made of tantalum, both of which may be formed by performing sequential conformal deposition processes, e.g., ALD, physical vapor deposition (PVD), etc. Other materials, such as cobalt and ruthenium, may be employed as part of the barrier layer/adhesion layer 46. Then, an illustrative layer of conductive material 48, e.g., copper, may be deposited in the openings 41 using traditional techniques.
FIG. 1H depicts the device after one or more CMP process operations were performed to remove the excess materials positioned outside of the openings 41 above the etch stop layer 44. This results in the formation of a conductive via 43 (VO) and a combination conductive via (VO)—metal line (M1) 45. Unfortunately, after the barrier layer/adhesion layer 46 is formed, portions of the void 31 may remain unfilled, as indicated in the dashed-line regions 50. Thus, there is an absence of the barrier layer/adhesion layer 46 under the conductive vias (VO), which can provide a path for undesired copper migration and otherwise undesirably locally increase the resistance of the connection at the interface between the via (VO) and the contact structure 32.
The present disclosure is directed to various methods of forming an improved interface between a conductive via and a conductive contact structure by selective formation of a conductive capping layer that may solve or at least reduce some of the problems identified above.